Beyond VHDL Simulation to On-Chip Testing Paper Views 415 Written by Francis Igot｜ Published on October 4, 2008 This paper is archived under Volume 18 / Number 4 (October – December 2008). Ronald J. Hayne Department of Electrical and Computer EngineeringThe Citadel Download PDF Francis IgotWebsite | + papersBio ⮌Francis Igothttps://coed.asee.org/author/francis-igot/Exploring Literate Programming in Electrical Engineering CoursesFrancis Igothttps://coed.asee.org/author/francis-igot/Analysis of Aircraft Actuator Failures within an Undergraduate Experiential Learning LaboratoryFrancis Igothttps://coed.asee.org/author/francis-igot/Simulation and Interactive Digital Tools to Support Teaching Engineering Manufacturing Processes CourseFrancis Igothttps://coed.asee.org/author/francis-igot/Promoting STEM to Middle School Girls through Coding and Fashion